Enhancement Type Of Mosfet

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Speaking of terminals, a MOSFET is typically a 3-terminal device, which are Gate (G), Source (S) and Drain (D) (even though there is a 4th terminal called Substrate or Body, it is usually not used in either input or output connection). MOSFET can be classified into Enhancement type MOSFET and Depletion type MOSFET. Fig 1: MOSFET (METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR) There are two basic types of MOSFET: 1.Enhancement-MOSFET. Here we are explaining most popular type, Enhancement-MOSFET or E-MOSFET. Structure of MOSFET. Like any other conventional transistor, A MOSFET is also made from a semiconductor material such as silicon. (b) Photograph of n-channel enhancement type MOSFET. From Fig 6.1 (a) it can be concluded that depletion type MOSFETs are normally ON type switches i.e, with the gate terminal open a nonzero drain current can flow in these devices. This is not convenient in many power electronic applications. Therefore, the enhancement type MOSFETs. Since the channel is nonexistent with VGS = 0 V and “enhanced” by the application of a positive gate-to-source voltage, this type of MOSFET is called an enhancement-type MOSFET. Both depletion type MOSFET and enhancement type MOSFET have enhancement-type regions, but the label was applied to the latter since it is its only mode of operation.

Two main types of FETs that presently exist are: JFETs and MOSFETs.

MOSFETs can be further classified into depletion type and enhancement type. Both these types define the fundamental mode of operation of MOSFETs, while the term MOSFET itself is the abbreviation of metal-oxide-semiconductor-field-effect transistor.

Due to the fact that the two types have different working characteristics, we'll be evaluating each of them separately in different articles.

Difference between Enhancement and Depletion MOSFET

Basically, unlike enhancement MOSFETs, depletion MOSFETs are in an on-state even in the presence of a 0 V across the gate-to-source terminals (VGS).

For an enhancement MOSFET, the gate-to-source voltage (VGS) must be above its gate-to-source threshold voltage (VGS(th)) in order to make it conduct.

However, for an N-channel depletion MOSFET, its VGS(th) value is above 0 V. This means that even if VGS = 0 V, a depletion MOSFET is able to conduct current. To turn it off, the VGS of a depletion MOSFET needs to be reduced below the VGS(th) (negative).

In this present article we'll discuss the depletion type MOSFET, which are said to have characteristics matching that of a JFET. The similarity is between cut-off and saturation near IDSS.

Basic Construction

Fig.5.23 shows the basic internal structure of a n-channel depletion-type MOSFET.

We can find a block of p-type material created using a silicon base. This block is called the substrate.

The substrate is the base or the foundation over which a MOSFET is constructed. For some MOSFETs it is internally linked with the 'source' terminal. Also, many devices offer an extra output in the form of SS, featuring a 4-terminal MOSFET, as revealed in Fig.5.23

The drain and the source terminals are connected through conductive contacts to n-doped locations, and attached through an n-channel, as indicated in the same figure.

The gate is also connected to a metallic layer, although it is insulated from the n-channel through a fine layer of silicon dioxide (SiO2).

SiO2 possesses a unique form of insulation property called dielectric which creates an opposing electric field within itself in response to an externally applied electric field.

Being an insulating layer, the material SiO2 offers us the following important information:

A complete isolation is developed between the gate terminal and the mosfet channel with this material.

Moreover, it is because of SiO2, the gate of the mosfet is able to feature an extremely high degree of input impedance.

P Channel Enhancement Mosfet

Due to this vital high input impedance property, the gate current IG is virtually zero amps for any dc-biased MOSFET configuration.

Basic Operation and Characteristics

AS can be seen in Fig.5.24, the gate to source voltage has been configured at zero volts by connecting the two terminals together, while a voltage VDS is applied across the drain and source terminals.

With the above setting, the drain side establishes a positive potential by the n-channel free electrons, along with an equivalent current through the JFET channel. Also, the resulting current VGS = 0V is still being identified as IDSS, as given in Fig. 5.25

We can see that in Fig.5.26 the gate source voltage VGS is given a negative potential in the form of -1V.

This negative potential tries to force electrons toward the p-channel substrate (since charges repel), and pull holes from the p-channel substrate (since opposite charges attract).

Depending on how large this negative bias VGS is, a recombination of holes and electrons takes place which results in the reduction of free electrons in the n-channel available for the conduction. Higher levels of negative bias results in higher rate of recombination.

The drain current consequently is reduced as the above negative bias condition is increased, which is proven in Fig.5.25 for VGS levels of VGS = -1, -2 and so forth, until the pinch-off mark of -6V.

The drain current as a result along with the transfer curve plot proceeds just like that of a JFET.

Now, for the positive VGS values, the gate positive will attract excess electrons (free carriers) from the p-type substrate, on account of the reverse leakage current. This will establish fresh carriers by the way of resultant collisions across the accelerating particles.

As the gate-to-source voltage tends to rise at the positive rate, the drain current shows a rapid increase, as proven in the Fig.5.25 for the same reasons as discussed above.

The gap developed between the curves of VGS = 0V and VGS = +1 distinctly shows the amount by which the current increased due to the 1 - V variation of the VGS

Due to the fast rise of the drain current we must be careful about the maximum current rating, otherwise it could cross the positive gate voltage limit.

For example, for the device type depicted in the Fig.5.25, applying a VGS = +4V would cause the drain current to rise at 22.2 mA, which may be crossing the maximum breakdown limit (current) of the device.

The above condition shows that the use of a positive gate-to-source voltage generates an enhanced effect on the quantity of the free carriers in the channel, as opposed to when VGS = 0V.

This is why the positive gate voltage region on the drain or transfer characteristics is generally known as enhancement region. This region lies between the cut-off and the saturation level of IDSS or the depletion region.

Solving an Example Problem

Advantages and Applications

In contrast to enhancement-mode MOSFETs, where we find the drain current dropping to zero in response to a zero gate-to-source voltage, the modern depletion-mode FET features noticeable current with zero gate voltage. To be precise, the drain-to-source resistance is usually 100 Ohms in zero voltage.

As indicated in the above graph, the ON-resistance rds(on) vs analogue signal range looks like a practically flat response. This characteristic, in conjunction with the low-capacitance levels of the these advanced depletion type device, allow them to be specifically ideal as analogue switches for audio and video switching applications.

The depletion-mode MOSFET's 'normally-on' attribute enables the device to be perfectly suitable for single FET current regulators.

One such example circuit can be seen in the following figure.

The Rs value could be determined using the formula:

Rs = VGSoff [ 1 - ( ID/IDSS)1/2] / ID

where ID is the amount of regulated current required at the output.

The main advantage of depletion-mode MOSFETs in current-source application is their minimal drain capacitance, that makes them appropriate for biasing applications in low-input leakage, medium- speed (>50 V/us) circuits.

The figure below exhibits a low-input-leakage current differential front-end using a double low-leakage function FET.

Generally speaking, either side of the JFET is going to be biased at ID = 500 uA. Therefore, the current obtainable for charging compensation and stray capacitances becomes restricted to 2ID or, in cases like this, 1.0 mA. The JFET's corresponding features are production-proven and assured on the datasheet.

Cs symbolizes the output capacitance of the input stage 'tail' current source. This capacitance is crucial in non-inverting amplifiers, due to the fact that the input stage experiences significant signal exchanges throughout this network, and the charging currents in Cs could be big. In case normal current sources are employed, this tail capacitance could be accountable for noticeable slew-rate deterioration in non-inverting circuits (compared to inverting applications, where the charging currents in Cs tend to be minimal).

The drop in the slew-rate could be expressed as:

1 / 1+ (Cs/Sc)

So long as Cs is lower than Cc (the compensation capacitor), there may be hardly any variation in the slew rate. Working with the DMOS FET, Cs can be around 2 pF. This strategy produces a huge improvement in the slew-rate. Where current deficits higher than 1 to 5 mA are needed, the device could be biased into the enhancement mode to generate as much as 20 mA for a maximum VGS of +2.5 V, with minimal output capacitance continuing to be a key aspect.

The next application below exhibits a proper enhancement-mode current source circuit.

A 'normally -on' analogue switch could be built for requirements where standard condition becomes necessary during a supply voltage failure, for example in automatic ranging of test tools or for ensuring accurate start-up of logic circuits at switch ON.

The reduced negative threshold voltage of the device offers basic drive prerequisites and permits working with minimal voltage.

The circuit below demonstrates the common bias factors for any depletion-mode DMOS analogue switch.

To cause the device to switch off, a negative voltages becomes necessary on the gate. Having said that, the on-resistance could be minimized when the FET is additionally enhanced using a positive gate voltage, enabling it specifically in the enhancement-mode region along with the depletion -mode region.

This response can be witnessed in in the following graph.

The high-frequency gain of the unit, together with its low capacitance values, delivers an increased 'figure of merit'. It is really an crucial element in VHF and UHF amplification, which specifies the gain-bandwidth product (GBW) of the FET, which could be depicted as:

GBW = gfs / 2π(Cin + Cout)

p-Channel Depletion-Type MOSFET

The construction of a p-channel depletion-type MOSFET is a perfect reverse of an n-channel version shown in Fig.5.23. Meaning, the substrate now takes the form of an n-type and the channel becomes a p-type, as can be seen in Fig.5.28a below.

The terminal identification remains unchanged, but the voltage and the current polarities are reversed, as indicated in the same figure. The drain characteristics would be exactly as depicted in Fig.5.25, except VDS sign which will in this case get a negative value.

The drain current ID shows a positive polarity in this case too, that's because we have already reversed its direction. VGS shows an opposite polarity, which is understandable, as indicated in Fig.5.28c.

Because VGS is reversed produces a mirror image for the transfer characteristics as indicated in Fig.5,28b.

Meaning, the drain current increases in the positive VGS region from the cut-off point at VGS = Vp until IDSS, then it continues to rise as the negative value of VGS rises.

Symbols

The graphical signs for an n- and p-channel depletion-type MOSFET can be witnessed in the above Fig. 5.29.

Observe the way the selected symbols aim to represent the true structure of the device.

The absence of a direct interconnection (because of the gate insulation) between the gate and channel is symbolized by a gap between the gate and the different terminals of the symbol.

The vertical line which represents the channel is attached between the drain and source and is “held” by the substrate.

Two groups of symbols are furnished in the figure above for each type of channel to highlight the fact that in some devices the substrate may be accessible externally while in others this may not be seen.

MOSFET (Enhancement-Type)

Although depletion type and enhancement type MOSFETs look similar with their internal structures and functional mode, their characteristics may be quite different.

Enhancement Type Of Mosfet

The main difference being the drain current which depends on a specific level of gate-to-source voltage for the cut off action.

Precisely, an n-channel enhancement-type MOSFET can work with a positive gate/source voltage, instead of a range of negative potentials which can normally impact a depletion type MOSFET.

Basic Construction

You can visualize the n-channel enhancement-type MOSFET in the following
Fig. 5.31.

A p-type material section is created through a silicon base, and as learned before it is termed as the substrate.

This substrate on some occasions is attached internally with the source pin in a depletion-type MOSFET, while in some instances it is terminated as a fourth lead for enabling an external control of its potential level.

The source and drain terminals are as usual joined using metallic contacts to n-doped regions.

However, it may be important to visualize that in Fig. 5.31 the channel between the two n-doped regions is missing.

This may be considered as the fundamental dissimilarity between a depletion-type and an enhancement-type MOSFET's internal layout, that is an absence of an inherent channel which is supposed to be a part of the device.

The SiO2 layer can be seen still prevalent, which ensures an isolation between the metallic base of the gate terminal and the region between the drain and source. However, here it can be witnessed standing separated from the p-type material section.

From the above discussion we can conclude that a depletion and enhancement MOSFET internal layout may have some similarities, except the missing channel between drain/source for an enhancement type of MOSFET.

Basic Operation and Characteristics

For an enhancement type MOSFET when a 0 V is introduced at its VGS, due to the missing n-channel (which is known to carry a lot of free carriers) causes a current output to be zero, which is quite unlike of a depletion type of MOSFET, having ID = IDSS.

In such a situation due to a missing path across drain/source terminals, large amounts of carriers in the form of electrons are unable to accumulate at drain/source (because of the n-doped regions).

Applying some positive potential at VDS, with VGS set at zero volts and the SS terminal shorted with the source terminal, we actually find a couple of reverse biased p-n junctions between the n-doped regions and the p-substrate to enable any notable conduction across drain to source.


In Fig. 5.32 shows a condition where VDS and VGS are applied with some positive voltage higher than 0 V, allowing the drain and gate to be at a positive potential with respect to the source.

The positive potential at the gate pushes the holes in the p-substrate along the edge of the SiO2 layer departing the location and entering deeper into the regions of the p-substrate, as shown in the above figure. This happens because of the like charges that repel each other.

This results in a depletion region being created close to the SiO2 insulating layer that is void of holes.

Despite of this, the p-substrate electrons which are the minority carriers of the material are pulled towards the positive gate and start gathering in the region close to the surface of the SiO2 layer.

Due to the insulation property of the SiO2 layer negative carriers allow the negative carriers from getting absorbed at the gate terminal.

As we increase the level of VGS, the electron density close to the SiO2 surface also increase, until finally the induced n-type region is able to allow a quantifiable conduction across drain/source.

The VGS magnitude that causes an optimal increase in the drain current is termed as the threshold voltage, signified by the symbol VT. In datasheets you will be able to see this as VGS(Th).

As learned above, due to the absence of a channel at VGS = 0, and 'enhanced' with the positive gate-to-source voltage application, this type of MOSFET are known as enhancement-type MOSFETs.

You will find that both depletion- and enhancement-type MOSFETs exhibit enhancement-type regions, but the term enhancement is used for the latter because it specifically works using an enhancement mode of operation.

Now, when VGS is pushed over the threshold value, the concentration of the free carriers will boost in the channel where it's induced. This causes the drain current to increase.

On the other hand, if we keep the VGS constant and increase the VDS (drain-to-source voltage) level, this will ultimately cause the MOSFET to reach its saturation point, as normally would also happen to any JFET or a depletion MOSFET.

As shown in Fig. 5.33 the drain current ID gets leveled off with the aid of a pinching-off process, indicated by the narrower channel towards the drain end of the induced channel.

By applying applying Kirchhoff’s voltage law to the MOSFET's terminal voltages in Fig. 5.33, we get:

If VGS is kept constant to a specific value, for example 8 V, and VDS is raised from 2 to 5 V, the voltage VDG by Eq. 5.11 could be seen dropping from -6 to -3 V, and the gate potential getting less and less positive with respect to the drain voltage.

This response prohibits the free carriers or electrons from getting pulled towards this region of the induced channel, which in turn results in a drop in the effective width of the channel.

Ultimately, the channel width decreases to the point of pinch-off , reaching a saturation condition similar to what we already learned in our earlier depletion MOSFET article.

Meaning, increasing the VDS any further with a fixed VGS does not affect the saturation level of ID, until the point where a breakdown situation is reached.

Looking at the Fig 5.34 we can identify that for a MOSFET as in Fig.5.33 having VGS = 8 V, saturation takes place at a VDS level of 6 V. To be precise the VDS saturation level is associated to the applied VGS level by:

No doubt, it thus implies that when the VT value is fixed, increasing the level of VGS will proportionately cause higher levels of saturation for VDS through the locus of saturation levels.

Referring to the characteristics shown in the above figure, the VT level is 2 V, which is evident by the fact that the drain current has fallen to 0 mA. Make macos usb.

Therefore typically we can say:

When VGS values are less than the threshold level for enhancement-type MOSFET, its drain current is 0 mA.

We can also clearly see in the above figure that as long as the VGS is raised higher from VT to 8 V, the corresponding saturation level for ID also increases from 0 to 10 mA level.

Moreover we can further notice that the space between the VGS levels increases with an increase in the value of VGS, causing an infinitely rising increments in drain current.

We find the drain current value is related to the gate-to-source voltage for VGS levels that's greater than VT, through the following nonlinear relationship:

The term which is shown squared bracket is the term which is responsible for the nonlinear relatinship between ID and VGS.

The term k is a constant and is a function of the MOSFET layout.

We can find out the value of this constant k through the following equation:

where the ID(on) and VGD(on) each are values specifically depending on the characteristic of the device.

In the next Fig. 5.35 below we find the drain and transfer characteristics are arranged one beside the other to clarify the transfer process across one another.

Basically, it is similar to the process explained previously for JFET and depletion-type MOSFETs.

Enhancement type mosfet equations

However, for the present case we have to remember that the drain current is 0 mA for VGS VT.

Here ID may see a noticeable amount of current, which will increase as determined by Eq. 5.13.

Note, while defining the points over the transfer characteristics from the drain characteristics, we only consider the saturation levels. This restricts the region of operation to VDS values higher than the saturation levels as established by Eq. (5.12).

p-Channel Enhancement-Type MOSFETs

The structure of a p-channel enhancement-type MOSFET as shown in Fig. 5.37a is just the opposite of that showing up in Fig. 5.31.

Meaning, , now you find that an n-type substrate and p-doped regions beneath the drain and source joints.

The terminals continue to be as established, but each of the current directions and the voltage polarities are reversed.

The drain characteristics can look like as given in Fig. 5.37c, having increasing amounts of current caused by a continuously more negative magnitudes of VGS.

The transfer characteristics would be the mirror impression (around the ID axis) of the transfer curve of Fig. 5.35, having ID increasing with more and more negative values of VGS above VT, as displayed in Fig. 5.37b. Equations (5.11) through (5.14) are similarly appropriate to p-channel devices.

References:

Working principle of an Field Effect Transistor

FET is a transistor in which current is controlled by varying the resistance of the channel from where the current is passing. The resistance is controlled by electric field.

Type of Field Effect Transistor

Depending upon the construction. FETs are divided into two categories

  1. Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET)

MOSFET Definition

MOSFET is very popular type of transistor which is a sub-category of field effect transistor. MOSFET full form is “ Metal Oxide Semiconductor Field Effect Transistor”. Just like JFET, it has three terminals gate (G), source (S) and drain (D). There is an insulating layer of silicon dioxide (SiO2) between the gate and the channel.

It has become a backbone of today’s modern technology products. Advanced microcontroller is based on MOSFET technology. One reason is that switching speed of mosfet transistors is fast as compared to BJT. The small size is another reason. These features are very important that is why its has extensive applications in electrical and electronics industry.

MOSFET Types

Mosfet transistor has further two types

    1. Enhancement MOSFET (E-MOSFET)
    2. Depletion MOSFET (D-MOSFET)

You can also watch this comprehensive tutorial to understand the basics

If You want to know more about these two types continue reading this article.

Enhancement MOSFET (E-MOSFET) Operation

Figure-1 explains the structure of enhancement MOSFET. For the sake of simplicity we are considering n-channel. The working of p-channel enhancement MOSFET is opposite to it.

The body of the E-MOSFET is made of p-type material which is also known as substrate. The body terminal and the source are usually connected internally. The n-type source and drain are diffused into the body of MOSFET.

Fig-1: MOSFET Construction

For the flow of current we apply positive voltage between the G and S. Please note If we apply the potential difference between the D and the S without applying any potential at the gate. The depletion region will increase subject to which terminal is at a higher potential (See Fig 2). For example If we connect the positive terminal of the battery with the drain and negative terminal with source. Depletion region between n-type drain and p-type substrate will be reverse biased and the junction between n-type source and p-type substrate will be forward biased. So no current will flow in that case. Similar is the case if we reverse the polarity.

Fig-2: Voltage applied between drain and source with gate voltage = 0

This is why we apply positive voltage at G. The positive voltage at G pulls free electrons of the substrate towards the gate but due to insulating SiO2 layer no electron can go into the gate. But the electrons start gathering near the gate (See Figure-3).

Fig-3: Electrons gather near gate

This creates a channel between the D and S within substrate.The width of the channel depends upon the positive voltage applied at the G. More positive voltage will create more electric field so more electrons will accumulate near the gate. As there is no direct or physical connection between the G and the substrate but the electric field between them is the cause of this channel. This is why it is also called induced channel of MOSFET. (See Fig-4)

Fig-4: Induced Channel MOSFET

Enhancement MOSFET Symbol

Depletion MOSFET (D-MOSFET) Operation

The main difference between depletion MOSFET and enhancement MOSFET is that in D-MOSFET the channel is already diffused during the manufacturing process. So channel is already there we don’t need to create it by applying potential difference at the gate.

Modes of operation of depletion type MOSFET

This works in following two modes

1. Depletion Mode

To operate in this mode we apply negative voltage at the gate in case of n-channel. The negative charge at the gate evacuate the free electrons in the channel. So more holes are created near the gate. You can compare this situation with parallel plate capacitor. Gate is one plate of the capacitor and channel is the other plate whereas SiO2 layer acts as dielectric. More negative voltage results in more depletion of electrons from the channel. This reduces the channel width and also the conductivity. You keep on decreasing the voltage a time will come when channel will be completely off and drain current will be zero. Figure-5 expresses this mode.

Fig-5: Depletion mode of n-channel D-MOSFET

2. Enhancement Mode

In this mode we apply positive voltage at the gate. This attracts electrons towards the gate. As a result, the conductivity of the MOS increases. Refer the figure-6 to understand this mode

Fig-6: Enhancement mode of n-channel D-MOSFET

Note: The working of p channel D-MOSFET in both modes is the same except the polarities are reversed.

Depletion MOSFET Symbol

MOSFET Characteristics and Parameters

Enhancement MOSFET Characteristics

You can observe in figure-7 there is no drain current below a threshold voltage (Vth). Below Vth the resistance is infinite. So we get no parameter in this area. After Vth the current increases significantly. The equation that represent E-MOSFET transfer characteristic curve is given below

Where gk is the gradient which can be found by using the following formula

ID(on) is provided on the data sheet depending upon the type of MOSFET.

Fig-7: N-channel E-MOSFET transfer curve

For the p-channel you give negative voltage at the gate so the curve is a reflection of the above curve i.e -VGS and -Vth.

Depletion MOSFET Characteristics

As we discussed above that D-MOSFET can be operated by applying positive as well as negative voltage at the gate. Figure-8 shows the transfer curve for n-channel D-MOSFET. Recall this curve is just a replica of transconductance curve of JFET. So the same square law equation is applicable here.

Fig-8: N-channel D-MOSFET transfer curve

MOSFET Biasing Techniques

Biasing means basically the way or ways with which we can put an electronic device into working. The biasing of MOSFET is done by the following ways

  1. Zero-Bias
  2. Voltage-Divider Bias
  3. Drain-Feedback Bias

Enhancement MOSFET Biasing

It is clear from the fig-7 that E-MOSFET will not work before threshold voltage. So instead of zero bias we will use two other methods to bias E-MOSFET.

Voltage Divider Bias

E-MOSFET (n-channel) circuit diagram as voltage divider bias is given below

Fig-9: N-channel E-MOSFET Voltage Divider Circuit

We applied positive voltage at the drain because this is n-channel MOSFET for the p-channel we will apply negative voltage as we discussed above. This positive voltage is greater than Vth.

The voltage at the gate is

And drain to source voltage can be calculated as

The ID can be calculated from equation (1)

Drain-Feedback Biasing

In this biasing state, feedback is taken from the drain and given to the gate. The circuit is given below

Fig-10: Common Source Drain Feedback Biasing

Depletion MOSFET Biasing

A simple method of biasing D-MOSFET is used also known as self-bias method. If you observe in transfer curve of D-MOSFET in figure-8 above. You will see that max current ( IDSS ) passes between drain and source when VGS = 0. (See Fig-11)

Apple recommended mac cleaner. Fig-11: D-MOSFET Biasing

Operating regions of MOSFET

Similar to JFET, MOSFET operations can be explained in three regions given below.

1. Cutoff Region

In the cutoff region there is no current flows through the MOS device. In case of n-channel mosfet. When VGS is less than Vth then no channel forms or in other words negligible amount of current flows from drain to source

But in the case of p-channel we give negative voltage at the gate. So cut off region is above the Vth.

2. Linear Region

This region also known as Ohmic region. When VGS is greater than or equal to Vth, channel forms. The current starts flowing if drain voltage is greater the source. The VDS must be lesser than VGS– Vth.

For the p-channel everything explained in the above paragraph should be reversed to achieve linear region.

3. Saturation Region

If you increase VDS such that VDS>VGS – Vth, then n-channel MOSFET goes into saturation. Means further increment on VDS doesn’t increase ID.

MOSFET Handling Techniques

The gate the insulated so high input resistance and capacitance can accommodate very high static charge. This charge can damage the MOSFET. That is why one should be aware that how to handle MOSFET when used in a circuit.

  1. Usually a wire ring is rounded on the MOSFET leads. Don’t remove them until you are just going to install it in the circuit. Otherwise if leads touched each other, leakage current from the gate can damage the device
  2. Don’t remove MOSFET device when the circuit is ON
  3. All testing instruments should be grounded to earth ground.

MOSFET vs BJT

There are many reasons we can compare between both types of transistors

  1. BJT contains both types of currents i.e hole and electrons. In other words you can say the current contains both majority and minority carriers. Whereas in MOSFET most of the current consist of majority carriers.
  2. The input resistance of MOSFET is very high as compared to BJT. You can observe from the above discussion on MOSFET, the resistance is almost infinite because gate is insulated from the body of the MOSFET. That is why MOSFETs are good amplifiers as compared to BJTs.
  3. MOSFET are smaller in size as compared to BJT. So one BJT can be replaced by many MOSFETs. Small size is one of the major reasons software speed.
  4. MOSFETs consume less power as compared to BJTs. BJTs have constant voltage drop equal to their barrier potential.

Some Common Questions and Their Answers

Why MOSFET is called IGFET?

IGFET means “Insulated Gate Field Effect Transistor”. As you can see in figure-1 above the gate is insulated from the main channel with SiO2 layer. Thats is why it is called IGFET.

Why MOSFET is a majority carrier device?

If you remember BJT current flows from emitter to base and then to collector. In the case of NPN transistor electrons are majority carriers in emitter and they are the minority carriers in the base. So the current in BJT contains both minority and majority carriers. But if you observe above figures from fig-3 to fig-6. Either it is enhancement MOSFET (P or n- channel) or depletion MOSFET (p or n-channel) the channel is always made by one type of carriers (holes or electrons) which are in majority in the channel. That is why MOSFET is called a majority carrier device.

Why MOSFETis better than JFET?

Let’s compare n-channel MOSFET and JFET to understand this question. In case of n-channel JFET if we apply positive pulse at the gate the junction will be forward biased. This is undesirable because JFET is designed to work by reverse biasing the PN junction. In MOSFET the gate is insulated from the channel. But MOSFET is also sensitive to electrostatic charge.

Enhancement Mode Of Mosfet

Why MOSFET is called unipolar?

Because only one type of current passes through the channel i.e hole current or electronic current

N Channel Enhancement Mosfet Pdf

Who invented MOSFET?

Muhammad Atalia and Dawon Kahng invnted MOSFET in Nov 1959.

P Channel Enhancement Mode Mosfet

When does MOSFET turn on?

Enhancement Type Mosfet Notes

Every MOSFET has threshold value provided on the data sheet. Providing voltage greater than threshold voltage turns ON the MOS device.